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<oai_dc:dc schemaLocation="http://www.openarchives.org/OAI/2.0/oai_dc/ http://www.openarchives.org/OAI/2.0/oai_dc.xsd">
<dc:title>A Test Module for Aging Characterization of Digital Circuits</dc:title>
<dc:creator>Gata-Romero, José M.</dc:creator>
<dc:creator>Santana-Andreo, A.</dc:creator>
<dc:creator>Roca, Elisenda</dc:creator>
<dc:creator>Castro-López, R.</dc:creator>
<dc:creator>Fernández, Francisco V.</dc:creator>
<dc:contributor>Junta de Andalucía</dc:contributor>
<dc:contributor>Agencia Estatal de Investigación (España)</dc:contributor>
<dc:contributor>Ministerio de Ciencia e Innovación (España)</dc:contributor>
<dc:contributor>Gata-Romero, José M. [0009-0005-5782-1998]</dc:contributor>
<dc:subject>Accelerated aging tests | Bias Temperature Instability | characterization | Hot Carrier Injection | Ring Oscillators | variability</dc:subject>
<dc:description>Trabajo presentado en el International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), celebrado en Funchal (Portugal) del 3 al 5 de Julio de 2023. Copyright IEEE</dc:description>
<dc:description>In digital circuits, aging phenomena can lead to timing violations due to increased signal delays suffered by digital cells. An accurate and trustworthy characterization of these mechanisms in modern nanometer CMOS technologies is essential, for which accelerated aging tests are the typical experimental procedure used. This type of test makes it possible to observe aging degradation without waiting for years of circuit operation, by raising voltage and temperature conditions above their nominal values. These stress conditions have a major impact on how the cell under test will be affected by aging degradation. This paper presents a new highly versatile test module whose purpose is to generate AC and DC signals with different amplitudes and, in the case of AC signals, also with different frequencies, to stress a digital cell in a wide variety of scenarios.</dc:description>
<dc:description>This work was supported by grant ProyExcel_00536 funded by Consejería de Universidad, Investigación e Innovación of Junta de Andalucía. The work was also supported by grant PID2019-103869RB-C31 funded by MCIN/AEI/10.13039/501100011033, and by grant TED2021-131240B-I00 funded by MCIN/AEI/10.13039/501100011033 and by the “European Union NextGenerationEU/PRTR”. Andrés Santana Andreo was supported by grant PRE-2020-093167 funded by MCIN/AEI/10.13039/ 501100011033, and by “ESF Investing in your future”.</dc:description>
<dc:description>Peer reviewed</dc:description>
<dc:date>2024-04-24T17:33:37Z</dc:date>
<dc:date>2024-04-24T17:33:37Z</dc:date>
<dc:date>2023-07-31</dc:date>
<dc:type>Conference Paper</dc:type>
<dc:identifier>9798350332650</dc:identifier>
<dc:identifier>http://hdl.handle.net/10261/354897</dc:identifier>
<dc:identifier>10.1109/SMACD58065.2023.10192112</dc:identifier>
<dc:identifier>2-s2.0-85168706692</dc:identifier>
<dc:identifier>https://api.elsevier.com/content/abstract/scopus_id/85168706692</dc:identifier>
<dc:language>en</dc:language>
<dc:relation>#PLACEHOLDER_PARENT_METADATA_VALUE#</dc:relation>
<dc:relation>#PLACEHOLDER_PARENT_METADATA_VALUE#</dc:relation>
<dc:relation>#PLACEHOLDER_PARENT_METADATA_VALUE#</dc:relation>
<dc:relation>info:eu-repo/grantAgreement/Junta de Andalucia/ PLAN ANDALUZ DE INVESTIGACIÓN, DESARROLLO E INNOVACIÓN (PAIDI 2020)/ ProyExcel_00536/EXPLOTACIÓN DEL RTN PARA SEGURIDAD HARDWARE RESISTENTE AL ENVEJECIMIENTO (RTN-SECURE)</dc:relation>
<dc:relation>info:eu-repo/grantAgreement/AEI/Plan Estatal de Investigación Científica y Técnica y de Innovación 2017-2020/PID2019-103869RB-C31/ES/THE VARIABILITY CHALLENGE IN NANO-CMOS: FROM DEVICE MODELING TO IC DESIGN FOR MITIGATION AND EXPLOITATION (VIGILANT-IMSE)/</dc:relation>
<dc:relation>info:eu-repo/grantAgreement/AEI/PLAN ESTATAL DE INVESTIGACIÓN CIENTÍFICA, TÉCNICA Y DE INNOVACIÓN 2021-2023/TED2021-131240B-I00/ES VARIABILIDAD TEMPORAL EN CIRCUITOS INTEGRADOS: ENEMIGO (Y COMO COMBATIRLO PARA LA ECONOMIA CIRCULAR) Y AMIGO (Y COMO EXPLOTARLO PARA UNA SOLUCION DISRUPTIVA EN CIBERSEGURIDAD)</dc:relation>
<dc:relation>Proceedings - 2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuit Design, SMACD 2023</dc:relation>
<dc:relation>Postprint</dc:relation>
<dc:relation>https://doi.org/10.1109/SMACD58065.2023.10192112</dc:relation>
<dc:relation>Sí</dc:relation>
<dc:rights>open</dc:rights>
<dc:publisher>Institute of Electrical and Electronics Engineers</dc:publisher>
</oai_dc:dc>